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help_forum - modeling delays in SystemC [RE: [help_forum] About timed functional mode Message Thread: Previous | Next
  • To: "Shruti Patil" <shruti.patil@xxxxxxxxx>, "Markus Becker" <email@xxxxxxxx>, <help_forum@xxxxxxxxxxxxxxxxx>
  • From: "Vincent Motel" <vmotel@xxxxxxxxxxx>
  • Date: Sun, 30 Mar 2008 23:50:45 +0200
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Hi Shruti,

Yes, modeling delays is a very basic task in Verilog and VHDL, but is not so 
simple in SystemC, because there is no dedicated construct.

Here is a first possibility to model a delay with two simple SC_METHODs and a 
delayed event notification :

template<typename T>
class delay_inertial : public sc_module {
public:
  sc_in<T> in;
  sc_out<T> out;
  SC_HAS_PROCESS(delay_inertial);
  delay_inertial(sc_module_name name_, sc_time tdelay_) :
    sc_module(name_),
    tdelay(tdelay_),
    in("in"), out("out")
  {
    SC_METHOD(mi);
    sensitive << in.default_event();
    SC_METHOD(mo);
    sensitive << e;
  }
  sc_time tdelay;
  void mi() {
    val = in.read();
    e.cancel();
    e.notify(tdelay);
  }
  void mo() {
    out.write(val);
  }
  sc_event e;
  T val;
};

This is generic, and if your delay is 2 ns, it will work at with changes on the 
input at 0ns, at 3 ns ... but not with changes every 1 ns ! Because the values 
are only kept in one variable "val", which cannot retain all the changes that 
could happen during the delay. So any glitch of a of a duration smaller than 
the delay are filtered out.
That's why it is called "inertial delay" (like in the verilog/vhdl world).

Here is a way to model the equivalent of the "transport delay", that buffers 
any changes on the input signal and replicates them on the output after a delay 
:

template<typename T>
class delay_transport : public sc_module {
public:
  sc_in<T> in;
  sc_out<T> out;
  SC_HAS_PROCESS(delay_transport);
  delay_transport(sc_module_name name_, sc_time tdelay_) :
    sc_module(name_),
    tdelay(tdelay_),
    in("in"), out("out")
  {
    SC_METHOD(mi);
    sensitive << in.default_event();
    SC_THREAD(mo);
    sensitive << eq;
  }
  sc_time tdelay;
  void mi() {
    val = in.read();
    vq.push(val);
    eq.notify(tdelay);
  }
  void mo() {
    while(1) {
      wait();
      val = vq.front();
      out.write(val);
      vq.pop();
    }
  }
  sc_event_queue eq;
  std::queue<T> vq;
  T val;
};

The keys of that implementation are the std::queue<> to buffer the values, and 
the sc_event_queue to buffer the events corresponding to when the changes 
should happen on the output ('tdelay' after the corresponding event on the 
input).
[note that the sc_event_queue was not available in OSCI 2.0.1 SystemC, it 
appeared in 2.1]
I'm not sure delay_transport::mo() can be made a SC_METHOD, you may try that, 
with a dont_initialize().

I hope this answers your questions.

Best regards,

Vincent Motel
Cadence Design Systems


-----Original Message-----
From: Shruti Patil [mailto:shruti.patil@xxxxxxxxx] 
Sent: Sunday, March 30, 2008 10:26 PM
To: Markus Becker; help_forum@xxxxxxxxxxxxxxxxx
Subject: Re: [help_forum] About timed functional models

Hi Markus,

I am actually looking for some more generalization. The code you sent would 
definitely work for the type of problem I described. However, I am working with 
inputs which are not necessarily binary, but could have three values. For such 
inputs, wait(myInput.pos()) will not work.
Any change in myInput should result in a change in output just like any 
asynchronous module (with some delay).

I am looking for something which is an equivalent of wait(input1_name
|| input2_name) instead of wait(clock.pos()) in your code, where
input1_name and input2_name are events associated with any change in the state 
of input1 and input2 signals.

Shruti

On Sun, Mar 30, 2008 at 1:23 PM, Markus Becker <email@xxxxxxxx> wrote:
> Hi,
>
>  maybe it's just something like this you're looking for?
>
>  SC_RTOS_MODULE(A) {
>     sc_in_clk clock;
>     SC_CTOR(A) {
>         SC_THREAD(TaskA);
>     }
>
>     void TaskA (void) {
>
>         while(true){
>                 // wait on positive clock edge
>                 wait(clock.pos());
>
>                 // do some work...
>
>                 // wait for 2ns
>                 wait(2, SC_NS);
>
>         }
>
>     }
>  }
>
>  Regards,
>  Markus
>
>  -----Ursprüngliche Nachricht-----
>  Von: Shruti Patil [mailto:shruti.patil@xxxxxxxxx]
>  Gesendet: Sonntag, 30. März 2008 19:16
>  An: help_forum@xxxxxxxxxxxxxxxxx
>  Betreff: [help_forum] About timed functional models
>
>
>
>  Hi,
>
>  I have a very basic problem while adding processing delay to a module.
>
>  The module (Module A) should only trigger with changes in its inputs,  
> and after triggerring, it should generate output after 2 ns.
>
>  If I use sc-thread and use wait(2,SC_NS), the module will only sample  
> its inputs evey 2 ns, which means it will check for changes in inputs  
> at 0ns, 2ns, 4ns, 6ns, etc. So if inputs change at 3ns, it is only  
> seen at 4ns and 1ns is lost.
>
>  If I use sc_method, then i can't introduce a wait statement.
>
>  I looked up sc_event, but it seems sc_event can only be used within a  
> module and not across modules. Is that right? I have another module  
> (Module B) which should trigger once the output of this first module  
> changes. I don't know how to use the event of Module A as an input  
> port for module B.
>
>  Can someone help? Adding a processing delay does seem to be a very  
> basic task that can be one very easily in vhdl and verilog, without  
> compromising the sensitivity of the module. What does systemC have for  
> this purpose?
>
>  Thank you.
>
>  Shruti
>
>

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