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SystemC Verification Working Group (VWG)


The Verification Working Group (VWG) is responsible for defining verification extensions to the SystemC language standard, as well as enriching the SystemC reference implementation by offering an add-on SystemC Verification (SCV) library to ease the deployment of a verification methodology based on SystemC.

Chair: Stephan Schulz, Fraunhofer Institute For Integrated Circuits 

Vice Chair: Bas Arts, NXP Semiconductors

Current Status

On June 20, 2013, the SystemC Verification Working Group began a 90-day public review of the SystemC Verification Library 2.0, an update to SCV 1.0p2. This release contains an implementation of the verification extensions for Accellera Systems Initiative SystemC 2.3.0 and Accellera SystemC 2.2.0 and is compatible with IEEE 1666. Examples and support for recent compilers is also included. The document can be accessed here (acceptance of the SystemC Open Source License required).

  • Compatible with IEEE 1666-2011 through Accellera SystemC 2.3.0.
  • 64-bit support
  • Recent compilers support (Visual C++ 2088, GCC up to 4.7, clang)
  • Modern OS support (Windows 7, recent RHEL and Ubtuntu Linux, OS X)
  • Numerous bug fixes

The SystemC Verification Working Group encourages your review of the proposed SCV 2.0 documentation. Please email your feedback to The SCV Working Group will make every effort to properly assess and incorporate feedback received as it deems appropriate. Feedback should be submitted prior to September 20, 2013, to ensure time for incorporation into the final SystemC Verification Library 2.0 release. Feedback received after that date will still be considered, but may be delayed into a subsequent release of the standard.


SystemC is one of the key languages used for verification activities. Beyond SystemC’s built-in capabilities, verification extensions to its API are needed to avoid reinventing the same mechanism all over again and to provide a stable framework onto which tools suppliers can build added value. As SystemC is a system-level specification methodology, this includes the application of verification approaches on abstract levels, besides hardware potentially also covering RTOS and software.


The current SystemC Verification (SCV) library (version 1.0p2) already provides a common set of APIs that are used as a basis to verification activities with SystemC (generation of values under constraints, transaction recording, etc.). These APIs are implemented in all major SystemC simulators available on the market.

As verification needs in SystemC evolve and communication with other languages is more and more frequent, additions to the existing set of APIs are required. For example, these additions will also focus on coverage analysis and temporal assertion checking mechanisms and their interfacing and/or integration into the SystemC language. Standardizing these additions is crucial to allow seamless migration of models from the environment of one tool supplier to another. This integration process also includes the analysis and evaluation of interfaces to existing ASI verification approaches like UVM and their seamless integration into a SystemC-based verification process.

SCV 1.0p2 is compatible with SystemC 2.2 as well as the earlier SystemC V2.1v1.

Join this Working Group

If you are an employee of a member company and would like to join this working group, click here (requires login) and click Join Group. WG participation requires right of entry by the group chair.