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DVCon: The Imitation Game

What if I were to tell you that I attended a conference where people were really excited to be there, where the exhibit hall was filled with a crush of people making their way from booth to booth, talking with exhibitors and exchanging business cards madly. A conference where the South of the exhibit hall was dominated by Synopsys, the East by Cadence, and the West by Mentor, and where at the happiest hour, libations and snacks flowed freely in a sub-set of the booths and the whole exhibit hall became even more animated.

05 Mar 2015
Accellera Systems Initiative Forms Portable Stimulus Working Group

Proposed standard to specify verification intent and behaviors reusable across multiple target platforms

Electronic Engineering Journal
11 Feb 2015
Accellera Adds Portable Stimulus Group

Accellera created a working group for the portable test and stimulus, which would allow engineering teams to create the test once and be able to run it throughout the flow.

Semiconductor Engineering
11 Feb 2015
Intel's Shishpal Rawat: Multiple hats, Singular focus

Last week I had a chance to chat by phone with Accellera Chair Shishpal Rawat, and when I say chance that's accurate. Rawat is so busy these days, it's hard to believe he has time for any extraneous conversations. Not only does he have a full-time job at Intel, he has been chair of Accellera for four years and now is ramping up to take over the reins at CEDA at well.

25 Sep 2014
Accellera Updates UVM Standard

New verification standard readied for submission to IEEE; 90-day public comment period begins.

Semiconductor Engineering
01 Jul 2014
Accellera Enhances Mixed-signal Modeling and Verification in Verilog-AMS 2.4 Standard

Accellera announces it has developed new verification and design modeling extensions for its Verilog-AMS standard. Verilog-AMS provides powerful structural and behavioral modeling capabilities for mixed-signal designs in which the effects of, and interactions among, different disciplines such as electrical, mechanical, fluid dynamics and thermal are important.

Low-Power Design
03 Jun 2014
Accellera publishes SystemC-AMS 2.0 standard

Accellera Systems Initiative has published the language reference manual for the latest version of its mixed-signal simulation environment based on SystemC. Version 2.0 of SystemC-AMS adds support for more dynamic behaviors in the analog domain.

Tech Design Forum
20 Mar 2013
DVCon 2013: Engineers Question EDA Standards Leaders at Accellera "Town Hall" Meeting

Do design and verification engineers care about EDA standards? If the Accellera Systems Initiative "Town Hall" meeting at DVCon 2013 Feb. 25 is any indication, the answer is an emphatic yes. A packed audience attended a lively, hour-long meeting in which non-stop questions were answered by Accellera and IEEE standards developers.

Cadence Industry Insights Blog
25 Feb 2013
Master & Commander: DVCon's Stan Krolikoski

Now in its 25th year, DVCon is coming up in a couple of weeks in Silicon Valley. In terms of process nodes, 25 years is about twelve generations. In terms of dog years, it's about four generations. In terms of the life of Stan Krolikoski, however, 25 years is only part of one career. It's also the amount of time Stan's been going to DVCon, even though it had a different name when he attended the first such conference back in 1988.

06 Feb 2013
A look back on 2012: Accellera

Editor's note: While other respondents talked about standards, the response I got from Accellera was so complete that I want to publish it in its entirety.

An important principle of Accellera Systems Initiative is to encourage availability and adoption of next-general EDA and IP standards. To that end, Accellera has realized several accomplishments this year in the areas of technical achievements and standards; industry events; educational videos; and awards.

EE Times
13 Dec 2012
Accellera Systems rolls new SystemC Library

"Accellera Systems Initiative has released the version 2.3.0 of its SystemC open source proof-of-concept library. The offering comes free of charge to the global electronic design community, the organization noted.

Compatible with the newly revised IEEE 1666 Standard SystemC Language Reference Manual, announced by the IEEE Standards Association in November last year, version 2.3.0 provides a number features including support for transaction-level modeling (TLM), a critical approach to enable high level and more efficient design of complex ICs and SoCs in a single library, Accellera Systems stated."

EDN Asia
18 Jul 2012
Accellera Systems Initiative: team effort & SystemC Library 2.3

"This week, Accellera Systems Initiative is announcing a new version of its SystemC library, Version 2.3 to be exact. There hasn't been a new version since way back in 2005 with Version 2.1 (albeit 2.2, a bug-fix release, was published in 2006), so this is the culmination of a lot of hard work."

18 Jul 2012
DAC 2012: How Unified Coverage Interoperability Standard (UCIS) Will Ease IC Verification

Richard Goering's Blog

Cadence: Industry Insights
11 Jun 2012
European SystemC User's Group - Interview with Axel Braun TLM Central
28 Feb 2012
IEEE 1666 SystemC Language Standard for Electronic System-Level Design Now Available

Accellera Systems Initiative announced today that the IEEE Standards Association (IEEE-SA), a globally recognized standards-setting body within the IEEE, now offers the latest version of the IEEE 1666 "Standard SystemC Language Reference Manual," for download at no charge, as part of the IEEE Get program.

Wireless Design & Development
22 Feb 2012
DVCon 2012 Insider: Tech. Papers, Tutorials, Keynote, Industry Leaders Panel and Accellera Systems Initiative", Karen Bartleson, Gen. Chair DVCon2012

View from The Top Executive Interviews

21 Feb 2012
Top 10 Tips for Success with Formal Analysis - Part 2

This is the second in a series of three articles presenting the "top 10" tips for the successful use of formal analysis on IP and SoC projects.

EE Times
30 Jan 2012
Accellera puts next release of SystemC library up for review

Transaction-level modelling and system-level analysis are important tasks for any low-power design activity given the major savings that can be made at this level: simply stopping transactions from repeating needlessly pays big in terms of reducing circuit activity and, with it, energy usage.

So, a new release in the SystemC world is something to watch and version 2.3 of the library is the first to...

17 Jan 2012
Accellera Systems Initiative Announces Call for Nominations for 2012 Technical Excellence Award for EDA and IP Standards Contributions EDACafe
16 Jan 2012
EDA standards bodies Accellera, OSCI merge [Chinese] EETimes Taiwan
06 Jan 2012

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