Skip Nav
Home » Resources » Articles and Insights

Articles and Insights


 Gabe Moretti  

DVCon United States Highlights

By Gabe Moretti

March 25, 2015

The first “DVCon United States” was a success. It was the 27th Conference of the series and the first one with this name to separate it from the newer DVCon Europe and DVCon India, which following their successful first events last year, will be held again this year.
Overall attendance, including exhibit-only and technical conference attendees, was 932. If we count, as DAC does, exhibitors personnel then the total number of attendees is 1213. The conference attracted 36 exhibitors, including 10 exhibiting for the first time and 6 of them headquartered outside of the US. The technical presentations were very well attended, almost always with standing room only, thus averaging around 175 attendees per session. One cannot fit more in the conference rooms than the DoubleTree has space for. The other thing I observed was that there was almost no attendee traffic during the presentations. People took a seat and stayed for the entire presentation. Almost no one came in, listened for a few minutes and then left. In my experience this is not typical and points out that the goal of DVCon, to present topics of contemporary importance, was met.
Gabe Moretti  

DVCon 2015: Not to Be Missed

By Gabe Moretti

February 23, 2015

In February 2000 VHDL International (VI) and Open Verilog International (OVI) agreed to merge and form Accellera.  That year DVCon, which until 2003 was called HDLCon, took place with the format it had for the previous 12 years.  Started in 1988 as the co-location of the Verilog Users Group and the VHDL International Users Forum (VIUF), DVCon was successful since its inception.
The name DVCon derives from Design and Verification Conference, and its focus was, and in part still is, the development, use, and improvement of Hardware Description Languages.  This year's conference is the 27th and offers an expanded technical program.  In spite of the consolidation occurring in the industry the exhibit space has remained practically the same as last year.  Although this year there will be one less tutorial than the previous year, the breath of topics is larger.

Whitepaper: Advancing the SystemC Analog/Mixed-Signal (AMS) Extensions —Introducing Dynamic Timed Data Flow
By Martin Barnasconi, NXP Semiconductors and AMS Working Group Chair; Karsten Einwich, Fraunhofer IIS/EAS Dresden; Christoph Grimm, Vienna University of Technology; Torsten Maehne, Université Pierre et Marie Curie; and Alain Vachoux, École Polytechnique Fédérale de Lausanne

September 2011

To comply with demanding requirements and use cases (e.g., in automotive applications), new execution semantics and language constructs are being defined to facilitate a more reactive and dynamic behavior of the Timed Data Flow (TDF) model of computation as defined in the current SystemC AMS 1.0 standard. The proposed Dynamic TDF introduces fully complementary elements to enable a tighter time-accurate interaction between the AMS signal processing and control domain while keeping the modeling and communication abstract and efficient. The features of Dynamic TDF are presented in this paper by means of a typical example application from the automotive domain.

Read more >

Martin Barnasconi     

Whitepaper: SystemC AMS Extensions—Solving the Need for Speed
By Martin Barnasconi, AMS Working Group Chair
May 2010

Similar to Transaction-level Modeling (TLM), the SystemC AMS extensions introduce smart methods to abstract time and uses known techniques to abstract signal properties. However, analog behavior is continuous in time and continuous in value, captured in an equation system and often seen as difficult to abstract. Any abstraction method applied would result in a less accurate description of the analog behavior. This is not necessarily a problem, as long as the abstracted behavior does not impact the essential characteristics or functionality of the AMS system for the intended application. So, when applying these abstraction methods in a smart manner, a major improvement in simulation speed is obtained, enabling totally new AMS analysis and verification methods through simulation, which have never been exercised before.

Read more >

Michael Meredith and Steve Svoboda     

The Next IC Design Methodology Transition Is Long Overdue
By Michael Meredith and Steve Svoboda, February 2010

Given that the RTL design abstraction has been in use for more than 15 years, it is no longer possible to consider it the leading-edge design approach that is required to bring us new, exciting consumer and industrial electronic products. Fortunately the move to the next level of abstraction using high-level synthesis in SystemC is well underway, and is demonstrating that it can deliver the required productivity.

Read more >

Martin Barnasconi     

Viewpoint: Analog/Mixed-Signal (AMS) extensions for SystemC
By Martin Barnasconi, AMS Working Group Chair
February 2009

The AMS draft 1 standard focuses on the system-level and architecture modeling aspects of designing and verifying complex AMS systems. By having AMS extensions for SystemC, users can build an executable description of the AMS system in a C++ based manner, enabling seamless integration with HW/SW architectures in SystemC and functional models or software developed in C and C++. As such, the AMS extensions should not be considered as a replacement of existing hardware description languages, but should be seen as a valuable addition to ESL design methodologies.

Read more >

Bart Vanthournout     

An Insider’s View on the Making of the New TLM-2.0 Standard
By Bart Vanthournout, TLM Working Group Chair
June 2008

Why is TLM-2.0 so important? TLM-2.0 standard interfaces for SystemC provides an essential framework needed for model exchange within companies and across the IP supply chain for architecture analysis, software development and performance analysis, and hardware verification. It explicitly addresses virtual prototyping in which SystemC models can easily be exchanged and arranged within a system. By providing a strong modeling foundation for virtual prototyping, the standard enables optimal reuse of models and modeling effort across different use cases.

Read more >