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Increasing Productivity with SystemC in Complex System Design and Verification
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2/25/13
Presented by experienced users and tool developers at the Design and Verification Conference (DVCon) 2013, this five-part video screencast delves into the interdisciplinary use of SystemC in building verification environments that provide early hardware access to software developers.
The tutorial is split into five parts:
- Configuration, Control & Inspection Working Group Update
- A SystemC Technology Demonstrator using the Xilinx Zynq™-7000
- A Unified Design Flow for SystemC Virtual Platforms and High-Level Synthesis
- From Virtual Prototyping to RTL Verification
- Virtual Prototyping: You don't need a PHD to model in System C and TLM
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